die d atasheet ga50jt06 - cal feb 2015 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 1 of 9 normally ? off silicon carbide junction transistor features ? 210 c maximum operating temperature ? gate oxide free sic switch ? exceptional safe operating area ? excellent gain linearity ? temperature independent switching performance ? low output capacitance ? positive temperature co - efficient of r ds,on ? suitable for connecting an anti - parallel diode die size = 4.35 mm x 4.35 mm advantages applications ? compatible with si mosfet/igbt gate - drivers ? > 20 s short - withstand capability ? lowest - in - class conduction losses ? high circuit efficiency ? minimal input signal distortion ? high amplifier bandwidth ? down hole oil drilling, geothermal instrumentation ? hybrid electric vehicles (hev) ? solar inverters ? switched - mode power supply (smps) ? power factor correction (pfc) ? induction heating ? uninterruptible power supply (ups) ? motor drives absolute maximum ratings (t c = 25 o c unless otherwise specified) parameter symbol conditions values unit drain ? source voltage v ds v gs = 0 v 6 00 v continuous drain current i d t c = 25c 10 0 a continuous drain current i d t c > 125c, assumes r thjc < 0.26 o c/w 50 a gate peak current i g m 3.5 a turn - off safe operating area rbsoa t vj = 210 o c, clamped inductive load i d,max = 50 @ v ds v dsmax a short circuit safe operating area scsoa t vj = 210 o c, i g = 1 a, v ds = 400 v, non repetitive 20 s reverse gate ? source voltage v gs 30 v reverse drain ? source voltage v ds 25 v operating junction and storage temperature t j , t stg - 55 to 210 c maximum processing temperature t proc 10 min. maximum 325 c electrical characteristics parameter symbol conditions values unit m in . t yp . m ax. on characteristics drain ? source on r esistance r ds(on) i d = 50 a, i g = 100 0 ma, t j = 25 c i d = 50 a, i g = 100 0 ma, t j = 1 25 c i d = 50 a, i g = 20 00 ma, t j = 17 5 c i d = 50 a, i g = 20 00 ma, t j = 210 c 25 39 m 43 62 gate ? source saturation voltage v gs,sat i d = 50 a, i d /i g = 40, t j = 25 c 3.42 v i d = 50 a, i d /i g = 30, t j = 175 c 3.23 dc current gain v ds = 5 v, i d = 50 a , t j = 25 c v ds = 5 v, i d = 50 a , t j = 1 25 c v ds = 5 v, i d = 50 a , t j = 17 5 c v ds = 5 v, i d = 50 a , t j = 210 c 105 77 71 69 off characteristics drain leakage current i dss v r = 6 00 v, v gs = 0 v, t j = 25 c 10 a v r = 6 00 v, v gs = 0 v, t j = 210 c 100 gate ? source leakage current i gss v gs = - 20 v , t j = 25 c 2 0 na v ds = 6 00 v r ds(on) = 25 m i d @ 25 o c = 100 a h fe = 105
die d atasheet ga50jt06 - cal feb 2015 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 2 of 9 electrical characteristics parameter symbol conditions values unit min. typ. max. capacitance characteristics input capacitance c is s v gs = 0 v, v d = 100 v, f = 1 mhz 6440 pf reverse transfer/output capacitance c rss /c oss v d = 100 v, f = 1 mhz 420 pf figures figure 1: t ypical output characteristics at 25 c figure 2: typi cal output characteristics at 12 5 c figure 3 : typi cal output characteristics at 17 5 c figure 4 : typi cal output characteristics at 210 c
die d atasheet ga50jt06 - cal feb 2015 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 3 of 9 figure 5 : typical gate ? source saturation voltage figure 6: normalized on - resistance and current gain vs. temperature figure 7 : typical blocking characteristics figure 8 : capacitance characteristics
die d atasheet ga50jt06 - cal feb 2015 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 4 of 9 driving the ga50jt06 - cal drive topology gate drive power consumption switching frequency application emphasis availability ttl logic high low wide temperature range coming soon constant current medium medium wide temperature range coming soon high speed ? boost capacitor medium high fast switching production high speed ? boost inductor low high ultra fast switching coming soon proportional lowest high wide drain current range coming soon pulsed power medium n/a pulse power coming soon a: static ttl logic driving the ga 50jt06 - cal may be driven using direct (5 v) ttl logic after current amplification. the (amplified) current level of the supply must meet or exceed the steady state gate current (i g,steady ) required to operate the ga 50jt06 - cal. the power level of the supply can be estimated from the target dut y cycle of the particular application. i g,steady is dependent on the anticipated drain current i d through the sjt and the dc current gain h fe , it may be calculated from the following equation. an accurate value of the h fe may be read from figure 6 . ? ? , ? ????? ? ? ? ?? ( ? , ? ? ) ? 1 . 5 figure 9 : ttl gate drive schematic b: high speed driving the sjt is a current controlled transistor which requires a positive gate current for turn - on as well as to remain in on - state. an ideal gate current waveform for ultra - fast switching of the sjt, while maintaining low gate drive losses, is shown in figure 10 which features a positive current peak during turn - on, a negative current peak during turn - off, and continuous gate current to remain on. figure 10 : an idealized gate current waveform for fast switching of an sjt. an sjt is rapidly switched from its blocking state to on - state, when the necessary gate charge, q g , for turn - on is supplied by a burst of high gate current, i g,on , until the gate - source capacitance, c gs , and gate - drain capacitance, c gd , are fully charged. ? ?? = ? ? , ?? ? ? 1 ? ?? ? ?? + ? ?? sic sjt d s g ttl gate signal 5 / 0 v ttl i/p i g,steady 5 v
die d atasheet ga50jt06 - cal feb 2015 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 5 of 9 ideally, i g,on should terminate when the drain voltage falls to its on - state value in order to avoid unnecessary drive losses during the steady on - state. in practice, the rise time of the i g,on pulse is affected by the parasitic inductances, l par in the device package and drive circuit. a voltage developed across the parasitic inductance in the source path, l s , can de - bias the gate - source junction, when high drain currents begin to flow through the device. the voltage applied to the gate pin should b e maintained high enough, above the v gs,sat (see figure 5 ) level to counter these effects. a high negative peak current, - i g,off is recommended at the start of the turn - off transition, in order to rapidly sweep out the injected carriers from the gate, and achieve rapid turn - off. while satisfactory turn off can be achieved with v gs = 0 v, a negative gate voltage v gs may be used in order to speed up the turn - off transition. two high - speed drive topologies for the sic sjts are presented below. b:1: high speed, low loss drive with boost capacitor, ga15iddjt22 - fr4 the ga50jt17 - cal may be driven using a high speed, low loss drive with boost capacitor topology in which multiple voltage levels, a gate resistor, and a gate capacitor are used to provide fa st switching current peaks at turn - on and turn - off and a continuous gate current while in on- state. an evaluation gate drive board ( ga15iddjt22 - fr4 ) utilizing this topolog y is commercially available for low - side driving, its datasheet provides additional details. figure 1 : topology of the ga15iddjt22 - fr4 two voltage source gate driver. the ga15iddjt22 - fr4 evaluation board comes equipped with two on board gate drive resistors (rg1, rg2) pre - installed for an effective gate resistance 3 of r g = 0.7 ?. it may be ne cessary for the user to reduce rg1 and rg2 under high drain current conditions for safe operation of the ga50jt17 - cal. the steady state current supplied to the gate pin of the ga50jt17 - cal with on - board r g = 0.7 ?, is shown in figure 25 . the maximum allowable safe value of r g for the user?s required drain current can be read from figure 26 . for the ga50jt17 - cal, r g must be reduced for i d ~60 a for safe operation with the ga15iddjt22 - fr4 . for operation at i d ~60 a, r g may be calculated from the following equation, which c ontains the dc current gain h fe ( figure 4 ) and the gate - source saturation voltage v gs,sat ( figure 7 ) . ? ? ??? ? ? ? ? ?? ??? ? ? ? ?? ? ? ? ? ? ? ? i g cg2 sjt v gh d1 r5 r1 u4 v gl v ee v gl x2 v gh x1 v ee c2 c1 v ee u2 v gl v ee cg1 rg1 rg2 r2 c5 c21 c8 c9 c6 c7 +12 v +12 v vcc high vcc high rtn vcc low vcc low rtn signal signal rtn gate source gate driver board r3 r4 u1 u3 c4 v gl v ee c10 r6 d s g
die d atasheet ga50jt06 - cal feb 2015 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 6 of 9 figure 2 : typical steady state gate current supplied by the ga15iddjt22 - fr4 board for the ga50jt17 - cal with the on board resistance of 0.7 ? figure 3 : maximum gate resistance for safe operation of the ga50jt17 - cal at different drain currents using the ga15iddjt22 - fr4 board. b:2: high speed, low loss drive with boost inductor a high speed, low - loss driver with boost inductor is also capable of driving the ga 50jt06 - cal at high - speed. it utilizes a gate drive inductor instead of a capacitor to provide the high - current gate current pulses i g,on and i g,off . during operation, inductor l is charged to a specified i g,on current value then made to discharge i l into t he sjt gate pin using logic control of s 1 , s 2 , s 3 , and s 4 , as shown in figure 14 . after turn on, while the device remains on the necessary steady state gate current i g,steady is supplied from source v cc through r g . please refer to the article ?a current - so urce concept for fast and efficient driving of silicon carbide transistors by dr. jacek r?bkowski for additional information on this driving topology. 4 figure 14 : simplified inductive pulsed drive topology 3 ? r g = (1/ rg1 +1/rg2) - 1 . driver is pre - installed with rg1 = rg2 = 7.5 ? 4 ? archives of electrical engineering. volume 62, issue 2, pages 333 ? 343, issn (print) 0004 - 0746, doi: 10.2478/aee - 2013 - 0026 , june 2013 sic sjt d s g l r g v ee v cc v cc v ee s 1 s 2 s 3 s 4
die d atasheet ga50jt06 - cal feb 2015 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 7 of 9 c: proportional gate cur rent driving for applications in which the ga 50jt06 - cal will operate over a wide range of drain current conditions, it may be beneficial to drive the device using a proportional gate drive topology to optimize gate drive power consumption. a proportional gate driver relies on instantaneous drain current i d feedback to vary the steady state gate current i g,steady supplied to the ga 50jt06 - cal c:1: voltage controlled proportional driver the voltage controlled proportional driver relies on a gate drive ic to detect the ga 50jt06 - cal drain - source voltage v ds during on - state to sense i d . the gate drive ic will then increase or decrease i g,steady in response to i d . this allows i g,steady , and thus the gate drive power consumption, to be reduced while i d is relative ly low or for i g,steady to increase when is i d higher. a high voltage diode connected between the drain and sense protects the ic from high - voltage when the driver and ga 50jt06 - cal are in off - state. a simplified version of this topology is shown in figure 15 , additional information will be available in the future at http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/ figure 15 : simplified voltage controlled proportional driver c:2: current controlled proportional driver the current controlled proportional driver relies on a low - loss transformer in the drain or source path to provide feedback i d of the ga 50jt06 - cal during on - state to supply i g,steady into the device gate. i g,steady will then increase or decrease in response to i d at a fixed forced current gain which is set be the turns ratio of the transformer, h force = i d / i g = n 2 / n 1 . ga50jt 06- cal is initially tuned - on using a gate current pulse su pplied into an rc drive circuit to allow i d current to begin flowing. this topology allows i g,steady , and thus the gate drive power consumption, to be reduced while i d is relatively low or for i g,steady to increase when is i d higher. a simplified version o f this topology is shown in figure 16 , additional information will be available in the future at http://www.genesicsemi.com/commercial - sic/sic - junction - transistors/. figure 16 : simplified current controlled proportional driver sic sjt proportional gate current driver d s g gate signal i g,steady hv diode sense signal output sic sjt d s g n 2 n 2 n 1 n 3 gate signal
die d atasheet ga50jt06 - cal feb 2015 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 8 of 9 mechanical parameters die dimensions 4.35 x 4.35 mm 2 171 x 171 mil 2 die area total / active 18.92 / 16.56 mm 2 29330/25677 mil 2 die thickness 360 m 14 m il wafer size 100 mm 3937 mil flat position 0 deg 0 deg die frontside passivation polyimide gate/source pad metallization 40 00 nm al bottom drain pad metallization 400 nm ni + 200 nm au die attach electrically conductive glue or solder wire bond al 12 mil (source) al 5 mil (gate) reject ink dot size 0.3 mm recommended storage environment store in original container, in dry nitrogen, < 6 months at an ambient temperature of 23 c chip dimensions: mm mil die a 4.35 171 b 4.35 171 source wire bondable c 3.30 130 d 1.75 69 e 0.24 9 gate wire bondable f 0. 46 18 g 0. 57 22 a c f e d b g d
die d atasheet ga50jt06 - cal feb 2015 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 9 of 9 revision history date revision comments supersedes 2015/02/09 3 updated electrical characteristics 2014/0 8 /2 6 2 updated electrical characteristics 2014/03/03 1 updated electrical characteristics 2013/12 /0 4 0 initial release published by genesic semiconductor, inc. 43670 trade center place suite 155 dulles, va 20166 genesic semiconductor, inc. reserves right to make changes to the product specifications and data in this document without notice . genesic disclaims all and any warranty and liability arising out of use or application of any product. no license, express or implied to any intellectual property rights is granted by th is document. unless otherwise expressly indicated, genesic products are not designed, tested or authorized for use in life - saving, medical, aircraft n avigation, communication, air traffic control and weapons systems, nor in applications where their failure may result in death, personal injury and/or property damage.
die d atasheet ga50jt06 - cal mar 2014 http://www.genesicsemi.com/high - temperature - sic/high - temperature - sic - bare - die/ pg 1 of 1 spice model parameters this is a secure document. please copy this code from the spice model pdf file on our website http://www.genesicsemi.com/images/hit_sic/baredie/sjt/ga50jt06 - cal_spice.pdf ) into ltspice (version 4) software for simulation of the ga50jt06 - cal. * model of genesic semiconductor inc. * * $revision: 1.1 $ * $date: 0 3 - mar- 2014 $ * * genesic semiconductor inc. * 43670 trade center place ste. 155 * dulles, va 20166 * * copyright (c) 2013 genesic semiconductor inc. * all rights reserved * * these models are provided "as is, where is, and with no warranty * of any kind either expressed or implied, including but not limited * to any implied warranties of merchantability and fitness for a * particular purpose." * models accurate up to 2 times rated drain current. * .model ga50jt06 npn + is 5.00e- 47 + ise 1.26e- 28 + eg 3.23 + bf 106 + br 0.55 + ikf 9000 + nf 1 + ne 2 + rb 0.26 + re 0.01 + rc 0.013 + cjc 2.3989e- 9 + vjc 2.8346223 + mjc 0.4846 + cje 6.026e- 09 + vje 3.17915435 + mje 0.52951635 + xti 3 + xtb - 1.2 + trc1 7.00e- 3 + vceo 600 + icrating 50 + mfg genesic_semiconductor * end of ga50jt06- cal spice model
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